This invention relates to a high-speed serial interface (HSSI) in a programmable logic device (PLD) in which individual interface cells can have multiple functions. More particularly, this invention relates to a modified HSSI “quad” whose elements or cells can function as clock-data recovery (CDR) modules or as phase-locked loops (PLLs) or clock management units.
It has become common for PLDs to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards—e.g., the XAUI (Extended Attachment Unit Interface) standard and other standards. A common implementation for the aforementioned XAUI standard involves groups, called “quads,” of four transceiver channels. Each quad typically shares one or more additional modules or cells called “clock management units” (CMUs), which may include one or more PLLs or other clock sources (e.g., a delay-locked loop (DLL)) and which provide clock standards for the other modules in the quad.
It would be desirable to be able to provide a PLD with a more flexible HSSI structure.